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| author | Jerome Brunet <jbrunet@baylibre.com> | 2017-08-31 15:52:20 +0200 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2017-09-05 21:05:00 +0200 |
| commit | 67e7607fcdf1fad10e9f183424e709c59713e45d (patch) | |
| tree | d083f78fa48c7f3e3042593e9f06c3b09f27a407 /arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | |
| parent | ARM64: dts: meson: remove cap-sd-highspeed from emmc nodes (diff) | |
| download | linux-67e7607fcdf1fad10e9f183424e709c59713e45d.tar.xz linux-67e7607fcdf1fad10e9f183424e709c59713e45d.zip | |
ARM64: dts: meson: add mmc clk gate pins
Add the pinctrl to switch mmc clk pins in gpio (pulled down) mode. This
is necessary to be able to gate the clk outside of the SoC while
keeping it running in the controller
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index d77e19591ee3..704b214e8894 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -194,7 +194,8 @@ &sd_emmc_a { status = "okay"; pinctrl-0 = <&sdio_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; #address-cells = <1>; #size-cells = <0>; @@ -220,7 +221,8 @@ &sd_emmc_b { status = "okay"; pinctrl-0 = <&sdcard_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdcard_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; bus-width = <4>; cap-sd-highspeed; @@ -238,7 +240,8 @@ &sd_emmc_c { status = "okay"; pinctrl-0 = <&emmc_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; bus-width = <8>; cap-mmc-highspeed; |