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| author | Mike Leach <mike.leach@linaro.org> | 2022-04-13 23:49:25 +0200 |
|---|---|---|
| committer | Sudeep Holla <sudeep.holla@arm.com> | 2022-04-14 10:02:57 +0200 |
| commit | e7676a00bc52b994960f89b118b0d548e4542372 (patch) | |
| tree | 759d90fcdb887427b324cf5e8d23bb37769fa506 /arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | |
| parent | arm64: dts: juno: Fix SCMI power domain IDs for ETF and CS funnel (diff) | |
| download | linux-e7676a00bc52b994960f89b118b0d548e4542372.tar.xz linux-e7676a00bc52b994960f89b118b0d548e4542372.zip | |
arm64: dts: juno: add CTI entries to device tree
Add Coresight Cross Trigger Interface(CTI) entries to the device tree
for all the Juno variants.
Link: https://lore.kernel.org/r/20220413214925.30359-1-mike.leach@linaro.org
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Diffstat (limited to 'arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi index eda3d9e18af6..2e43f4531308 100644 --- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi +++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi @@ -23,7 +23,7 @@ }; }; - etf@20140000 { /* etf1 */ + etf_sys1: etf@20140000 { /* etf1 */ compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20140000 0 0x1000>; @@ -82,4 +82,39 @@ }; }; + + cti_sys2: cti@20160000 { /* sys_cti_2 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20160000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<0 1>; + arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>; + arm,trig-out-sigs=<0 1>; + arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>; + arm,cs-dev-assoc = <&etf_sys1>; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-in-sigs=<2 3 4>; + arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>; + arm,trig-conn-name = "ela_clus_0"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs=<5 6 7>; + arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>; + arm,trig-conn-name = "ela_clus_1"; + }; + }; }; |