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| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2016-11-18 13:23:13 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2016-11-18 13:26:53 +0100 |
| commit | 74c78036d5b5970266fa2075a17c9b89cabf873e (patch) | |
| tree | dc16c9fb2f01d49a364e4ad570ece00a24ed6239 /arch/arm64/boot/dts/exynos | |
| parent | arm64: dts: exynos: TM2 - add support for JPEG codec device (diff) | |
| download | linux-74c78036d5b5970266fa2075a17c9b89cabf873e.tar.xz linux-74c78036d5b5970266fa2075a17c9b89cabf873e.zip | |
arm64: dts: exynos: TM2 - add support for MFC video codec device
This patch adds device nodes for MFC video codec device to Exynos5433 SoC
dtsi and proper initial clock configuration to TM2 dts.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/exynos')
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 5 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynos5433.dtsi | 32 |
2 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index 6f506dd11714..ce4178126272 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -196,6 +196,11 @@ <&cmu_top CLK_ACLK_GSCL_333>; }; +&cmu_mfc { + assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>; + assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>; +}; + &cmu_mscl { assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>, <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 1d47480f4104..64226d5ae471 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -856,6 +856,18 @@ iommus = <&sysmmu_jpeg>; }; + mfc: codec@152E0000 { + compatible = "samsung,exynos5433-mfc"; + reg = <0x152E0000 0x10000>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "pclk", "aclk", "aclk_xiu"; + clocks = <&cmu_mfc CLK_PCLK_MFC>, + <&cmu_mfc CLK_ACLK_MFC>, + <&cmu_mfc CLK_ACLK_XIU_MFCX>; + iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>; + iommu-names = "left", "right"; + }; + sysmmu_decon0x: sysmmu@0x13a00000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a00000 0x1000>; @@ -916,6 +928,26 @@ #iommu-cells = <0>; }; + sysmmu_mfc_0: sysmmu@0x15200000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x15200000 0x1000>; + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "pclk", "aclk"; + clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>, + <&cmu_mfc CLK_ACLK_SMMU_MFC_0>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_1: sysmmu@0x15210000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x15210000 0x1000>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "pclk", "aclk"; + clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>, + <&cmu_mfc CLK_ACLK_SMMU_MFC_1>; + #iommu-cells = <0>; + }; + serial_0: serial@14c10000 { compatible = "samsung,exynos5433-uart"; reg = <0x14c10000 0x100>; |