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authorAdam Ford <aford173@gmail.com>2020-11-26 11:45:34 +0100
committerShawn Guo <shawnguo@kernel.org>2020-12-01 02:49:39 +0100
commit6b5cd77371e5e34769284bfb058ff332ae278cc5 (patch)
tree05178952706d430b5e3b04cddbf73aa4e5a2c746 /arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
parentarm64: dts: imx8mn: Add node for SPDIF (diff)
downloadlinux-6b5cd77371e5e34769284bfb058ff332ae278cc5.tar.xz
linux-6b5cd77371e5e34769284bfb058ff332ae278cc5.zip
arm64: dts: imx8mm-beacon-som: Configure RTC aliases
On the i.MX8MM Beacon SOM, there is an RTC chip which is fed power from the baseboard during power off. The SNVS RTC integrated into the SoC is not fed power. Depending on the order the modules are loaded, this can be a problem if the external RTC isn't rtc0. Make the alias for rtc0 point to the external RTC all the time and rtc1 point to the SVNS in order to correctly hold date/time over a power-cycle. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
index 6b53830ddf74..8380fd4047d4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
@@ -4,6 +4,11 @@
*/
/ {
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &snvs_rtc;
+ };
+
usdhc1_pwrseq: usdhc1_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
@@ -218,7 +223,7 @@
reg = <0x50>;
};
- rtc@51 {
+ rtc: rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
};