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authorPeng Fan <peng.fan@nxp.com>2023-10-01 10:27:58 +0200
committerShawn Guo <shawnguo@kernel.org>2023-10-10 05:06:00 +0200
commitc1d0782b5fc305196c6b096eb38f56db22ef7df2 (patch)
tree4f8a133197b20e3bbbb1205caac1ce7c4b391a04 /arch/arm64/boot/dts/freescale/imx93.dtsi
parentarm64: dts: imx8ulp: update gpio node (diff)
downloadlinux-c1d0782b5fc305196c6b096eb38f56db22ef7df2.tar.xz
linux-c1d0782b5fc305196c6b096eb38f56db22ef7df2.zip
arm64: dts: imx93: update gpio node
Per binding doc, i.MX93 GPIO supports two interrupts and one register base, compatible with i.MX8ULP. The current fsl,imx7ulp-gpio compatible could work for i.MX93 in gpio-vf610.c driver, it is based on the base address are splited into two with offset added in device tree node. Now following hardware design, using one register base in device tree node. This may break users who use compatible fsl,imx7ulp-gpio to enable i.MX93 GPIO. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx93.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx93.dtsi28
1 files changed, 16 insertions, 12 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index d6f6aeb7da74..4a0d604fd0db 100644
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -956,11 +956,12 @@
};
gpio2: gpio@43810080 {
- compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
- reg = <0x43810080 0x1000>, <0x43810040 0x40>;
+ compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x43810000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX93_CLK_GPIO2_GATE>,
@@ -970,11 +971,12 @@
};
gpio3: gpio@43820080 {
- compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
- reg = <0x43820080 0x1000>, <0x43820040 0x40>;
+ compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x43820000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX93_CLK_GPIO3_GATE>,
@@ -985,11 +987,12 @@
};
gpio4: gpio@43830080 {
- compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
- reg = <0x43830080 0x1000>, <0x43830040 0x40>;
+ compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x43830000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX93_CLK_GPIO4_GATE>,
@@ -999,11 +1002,12 @@
};
gpio1: gpio@47400080 {
- compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
- reg = <0x47400080 0x1000>, <0x47400040 0x40>;
+ compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x47400000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clk IMX93_CLK_GPIO1_GATE>,