diff options
| author | Abel Vesa <abel.vesa@nxp.com> | 2019-02-28 22:42:45 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-03-19 09:44:51 +0100 |
| commit | 9b87ebb149afae0855572a0562df18ab45858c18 (patch) | |
| tree | 3b48755ac82971f2e3a0f598d6bff73b8a97023f /arch/arm64/boot/dts/freescale | |
| parent | arm64: dts: imx8mq: Add the clocks and the latencies for the A53 cores (diff) | |
| download | linux-9b87ebb149afae0855572a0562df18ab45858c18.tar.xz linux-9b87ebb149afae0855572a0562df18ab45858c18.zip | |
arm64: dts: imx8mq: Add the buck vdd_arm regulator
According to the schematics, this is a MP2147 switch converter
which is controlled by GPIO1_IO13. When set the gpio is set to
high the regulator output is set to 0.9V. When the gpio is set
to low the regulator output is set to 1V.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 54737bf1772f..afea110b70a3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -31,6 +31,34 @@ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + buck2_reg: regulator-buck2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_buck2>; + compatible = "regulator-gpio"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + states = <1000000 0x0 + 900000 0x1>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; }; &fec1 { @@ -203,6 +231,13 @@ }; &iomuxc { + pinctrl_buck2: vddarmgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 + >; + + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 |