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| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2019-04-05 19:30:02 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-04-11 08:59:10 +0200 |
| commit | de2a538b97a489bb67be7cdc44115d1c6a07e837 (patch) | |
| tree | a55a98ebe58e15dba16348da5b642225af3201b9 /arch/arm64/boot/dts/freescale | |
| parent | arm64: dts: imx8mq: Add a node for SRC IP block (diff) | |
| download | linux-de2a538b97a489bb67be7cdc44115d1c6a07e837.tar.xz linux-de2a538b97a489bb67be7cdc44115d1c6a07e837.zip | |
arm64: dts: imx8mq: Combine PCIE power domains
According to NXP's FAE feedback and a comment in ATF firmware, PCIE1
and PCIE2 power domains can't really be used independently. Due to
shared reset line both power domains have to be turned on at the same
time. Account for that quirk by combining PCIE power domains into a
single 'pgc_pcie' power domain.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mq.dtsi | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 0235967d1a2e..253d6d66af1a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -472,9 +472,25 @@ reg = <IMX8M_POWER_DOMAIN_MIPI>; }; - pgc_pcie1: power-domain@1 { + /* + * As per comment in ATF source code: + * + * PCIE1 and PCIE2 share the + * same reset signal, if we + * power down PCIE2, PCIE1 + * will be held in reset too. + * + * So instead of creating two + * separate power domains for + * PCIE1 and PCIE2 we create a + * link between both and use + * it as a shared PCIE power + * domain. + */ + pgc_pcie: power-domain@1 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_PCIE1>; + power-domains = <&pgc_pcie2>; }; pgc_otg1: power-domain@2 { |