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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2017-09-19 11:26:57 +0200 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-10-12 18:25:19 +0200 |
| commit | fc5c0b4d0783000794812eb510e5c8506f961d0a (patch) | |
| tree | abef53606b4cda008ad66091def3b06cf872ce58 /arch/arm64/boot/dts/freescale | |
| parent | PCI: layerscape: Add support for ls1012a (diff) | |
| download | linux-fc5c0b4d0783000794812eb510e5c8506f961d0a.tar.xz linux-fc5c0b4d0783000794812eb510e5c8506f961d0a.zip | |
arm64: dts: ls1012a: Add PCIe controller DT node
Add PCIe controller node for ls1012a platform.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index a7698ac7264b..fe1ea5d707a8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -478,5 +478,29 @@ msi-controller; interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; }; + + pcie@3400000 { + compatible = "fsl,ls1012a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 118 0x4>, /* controller interrupt */ + <0 117 0x4>; /* PME interrupt */ + interrupt-names = "aer", "pme"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; + }; }; }; |