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authorKefeng Wang <wangkefeng.wang@huawei.com>2016-04-08 09:27:11 +0200
committerWei Xu <xuwei5@hisilicon.com>2016-04-27 16:40:11 +0200
commitaa8d3e74f54d0af737c46c77de35b39d9a44592b (patch)
tree867d8ab49a63698f52bc8a70ddc41d37682bd626 /arch/arm64/boot/dts/hisilicon/hip06-d03.dts
parentarm64: dts: hip05: Add nor flash support (diff)
downloadlinux-aa8d3e74f54d0af737c46c77de35b39d9a44592b.tar.xz
linux-aa8d3e74f54d0af737c46c77de35b39d9a44592b.zip
arm64: dts: Add initial dts for Hisilicon Hip06 D03 board
The Hip06 soc has same cpu topology compared with Hip05, four clusters and each cluster has quard Cortex-A57, but with different IO part, like HNS, SAS and PCI, they are all upgraded. There are also not same in ITS, MBIGEN and SMMU, etc. This patch adds the initial dts for hip06 d03 board. Note, there is no serial, because the soc use LPC uart, the serial node is not needed. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch/arm64/boot/dts/hisilicon/hip06-d03.dts')
-rw-r--r--arch/arm64/boot/dts/hisilicon/hip06-d03.dts34
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
new file mode 100644
index 000000000000..f3e5323e430b
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
@@ -0,0 +1,34 @@
+/**
+ * dts file for Hisilicon D03 Development Board
+ *
+ * Copyright (C) 2016 Hisilicon Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ *
+ */
+
+/dts-v1/;
+
+#include "hip06.dtsi"
+
+/ {
+ model = "Hisilicon Hip06 D03 Development Board";
+ compatible = "hisilicon,hip06-d03";
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x00000000 0x0 0x40000000>;
+ };
+
+ chosen { };
+};
+
+&usb_ohci {
+ status = "ok";
+};
+
+&usb_ehci {
+ status = "ok";
+};