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| author | Grzegorz Jaszczyk <jaz@semihalf.com> | 2019-10-04 16:27:25 +0200 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-10-09 09:36:40 +0200 |
| commit | ddda843324f7d9a730fefcbefae3a575eb1a1bdf (patch) | |
| tree | b857d4f1895e6b549c2801e6fbd90693e4d1b0cd /arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | |
| parent | arm64: dts: marvell: Add support for AP807/AP807-quad (diff) | |
| download | linux-ddda843324f7d9a730fefcbefae3a575eb1a1bdf.tar.xz linux-ddda843324f7d9a730fefcbefae3a575eb1a1bdf.zip | |
arm64: dts: marvell: Add AP806-dual cache description
Adding appropriate entries to device-tree allows the cache description
to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index 62ae016ee6aa..09849558a776 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -22,6 +22,13 @@ enable-method = "psci"; #cooling-cells = <2>; clocks = <&cpu_clk 0>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; }; cpu1: cpu@1 { device_type = "cpu"; @@ -30,6 +37,20 @@ enable-method = "psci"; #cooling-cells = <2>; clocks = <&cpu_clk 0>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; }; |