diff options
| author | Vidya Sagar <vidyas@nvidia.com> | 2019-09-05 12:45:53 +0200 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2019-09-20 21:24:35 +0200 |
| commit | 09a0774a183d4d9fdfa3d6e471fe09982cac2702 (patch) | |
| tree | afb75a438f5fc9fdfca98ad9061327c45933dc39 /arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | |
| parent | arm64: tegra: Add configuration for PCIe C5 sideband signals (diff) | |
| download | linux-09a0774a183d4d9fdfa3d6e471fe09982cac2702.tar.xz linux-09a0774a183d4d9fdfa3d6e471fe09982cac2702.zip | |
arm64: tegra: Add PCIe slot supply information in p2972-0000 platform
Add 3.3V and 12V supplies regulators information of x16 PCIe slot in
p2972-0000 platform which is owned by C5 controller and also enable C5
controller.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 23597d53c9c9..d47cd8c4dd24 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -93,9 +93,11 @@ }; pcie@141a0000 { - status = "disabled"; + status = "okay"; vddio-pex-ctl-supply = <&vdd_1v8ao>; + vpcie3v3-supply = <&vdd_3v3_pcie>; + vpcie12v-supply = <&vdd_12v_pcie>; phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, |