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authorMikko Perttunen <mperttunen@nvidia.com>2021-09-16 16:55:16 +0200
committerThierry Reding <treding@nvidia.com>2021-10-06 20:17:00 +0200
commit78a058737b5e0efbd816363364944f5464ebff35 (patch)
tree3c0067ede2491ec4f453b2e5c503bb7c9a742018 /arch/arm64/boot/dts/nvidia/tegra194.dtsi
parentarm64: tegra: Add new USB PHY properties on Tegra132 (diff)
downloadlinux-78a058737b5e0efbd816363364944f5464ebff35.tar.xz
linux-78a058737b5e0efbd816363364944f5464ebff35.zip
arm64: tegra: Add NVDEC to Tegra186/194 device trees
Add a device tree node for NVDEC on Tegra186, and device tree nodes for NVDEC and NVDEC1 on Tegra194. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra194.dtsi')
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194.dtsi38
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 5fc77b966766..08513902a070 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1457,6 +1457,25 @@
interconnect-names = "dma-mem";
iommus = <&smmu TEGRA194_SID_HOST1X>;
+ nvdec@15140000 {
+ compatible = "nvidia,tegra194-nvdec";
+ reg = <0x15140000 0x00040000>;
+ clocks = <&bpmp TEGRA194_CLK_NVDEC1>;
+ clock-names = "nvdec";
+ resets = <&bpmp TEGRA194_RESET_NVDEC1>;
+ reset-names = "nvdec";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>;
+ interconnect-names = "dma-mem", "read-1", "write";
+ iommus = <&smmu TEGRA194_SID_NVDEC1>;
+ dma-coherent;
+
+ nvidia,host1x-class = <0xf5>;
+ };
+
display-hub@15200000 {
compatible = "nvidia,tegra194-display";
reg = <0x15200000 0x00040000>;
@@ -1570,6 +1589,25 @@
iommus = <&smmu TEGRA194_SID_VIC>;
};
+ nvdec@15480000 {
+ compatible = "nvidia,tegra194-nvdec";
+ reg = <0x15480000 0x00040000>;
+ clocks = <&bpmp TEGRA194_CLK_NVDEC>;
+ clock-names = "nvdec";
+ resets = <&bpmp TEGRA194_RESET_NVDEC>;
+ reset-names = "nvdec";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>;
+ interconnect-names = "dma-mem", "read-1", "write";
+ iommus = <&smmu TEGRA194_SID_NVDEC>;
+ dma-coherent;
+
+ nvidia,host1x-class = <0xf0>;
+ };
+
dpaux0: dpaux@155c0000 {
compatible = "nvidia,tegra194-dpaux";
reg = <0x155c0000 0x10000>;