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authorShazad Hussain <quic_shazhuss@quicinc.com>2023-05-26 15:31:17 +0200
committerBjorn Andersson <andersson@kernel.org>2023-05-27 03:12:26 +0200
commit07e3e17205794c8df6b55c65117ca6a6502a37d7 (patch)
tree34cd38c2faabbe6a1530798663daaeff1d2187f2 /arch/arm64/boot/dts/qcom/sa8775p.dtsi
parentarm64: dts: qcom: apq8096: fix fixed regulator name property (diff)
downloadlinux-07e3e17205794c8df6b55c65117ca6a6502a37d7.tar.xz
linux-07e3e17205794c8df6b55c65117ca6a6502a37d7.zip
arm64: dts: qcom: sa8775p: add the QUPv3 #0 and #3 node
Add zeroth and third instance of the QUPv3 engine to the sa8775p.dtsi. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526133122.16443-2-quic_shazhuss@quicinc.com
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sa8775p.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sa8775p.dtsi26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 07aeb8a8e97b..74bd5f323d96 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -548,6 +548,19 @@
};
};
+ qupv3_id_0: geniqup@9c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x9c0000 0x0 0x6000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x403 0x0>;
+ status = "disabled";
+ };
+
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
@@ -592,6 +605,19 @@
};
};
+ qupv3_id_3: geniqup@bc0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0xbc0000 0x0 0x6000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x43 0x0>;
+ status = "disabled";
+ };
+
ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;