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authorAdam Ford <aford173@gmail.com>2020-12-13 19:37:53 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2020-12-28 10:46:45 +0100
commit7e0fac6a0da54557230ac3898688f37392404cdf (patch)
tree8bd58d41419bf32b9f2773c042632a1f2164b898 /arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
parentarm64: dts: renesas: beacon: Don't make vccq_sdhi0 always on (diff)
downloadlinux-7e0fac6a0da54557230ac3898688f37392404cdf.tar.xz
linux-7e0fac6a0da54557230ac3898688f37392404cdf.zip
arm64: dts: renesas: beacon: Enable SPI
The baseboard routes the SPI to a header which can/will be configured at either the kit level or using device tree overlays. Because the baseboard be supporting more than one kit, enable at the baseboard level rather than a bunch of duplicates later. Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20201213183759.223246-14-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
index 987df78ec44e..cb316e736364 100644
--- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
+++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
@@ -478,6 +478,13 @@
};
};
+&msiof1 {
+ pinctrl-0 = <&msiof1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
+};
+
&ohci0 {
dr_mode = "otg";
status = "okay";
@@ -531,6 +538,11 @@
bias-pull-down;
};
+ msiof1_pins: msiof1 {
+ groups = "msiof1_clk_g", "msiof1_rxd_g", "msiof1_txd_g";
+ function = "msiof1";
+ };
+
pwm0_pins: pwm0 {
groups = "pwm0";
function = "pwm0";