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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2023-03-15 07:47:26 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-03-30 15:56:21 +0200 |
| commit | 05d11e2f4460752fa5f7ce7657e1b040056c1736 (patch) | |
| tree | a5fb352e06bdc5dfcb12184709c4c6db34051d8a /arch/arm64/boot/dts/renesas/r9a07g044.dtsi | |
| parent | arm64: dts: renesas: r8a779a0: Update CAN-FD to R-Car Gen4 compatible value (diff) | |
| download | linux-05d11e2f4460752fa5f7ce7657e1b040056c1736.tar.xz linux-05d11e2f4460752fa5f7ce7657e1b040056c1736.zip | |
arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodes
Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and
RZ/Five DMAC nodes.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230315064726.22739-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a07g044.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 79cffbf20c55..7b68bbebb5bd 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -740,9 +740,11 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; + clock-names = "main", "register"; power-domains = <&cpg>; resets = <&cpg R9A07G044_DMAC_ARESETN>, <&cpg R9A07G044_DMAC_RST_ASYNC>; + reset-names = "arst", "rst_async"; #dma-cells = <1>; dma-channels = <16>; }; |