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| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2017-11-08 12:15:50 +0100 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2017-11-08 12:15:50 +0100 |
| commit | 4e37fd4d5dfd39f547b0b00fa184a440a1e44b96 (patch) | |
| tree | 1f2a678cce5422703aa376ab3506f430d51f89da /arch/arm64/boot/dts/rockchip/rk3399.dtsi | |
| parent | ARM: cpuidle: Refactor rollback operations if init fails (diff) | |
| parent | PM / QoS: Fix device resume latency framework (diff) | |
| download | linux-4e37fd4d5dfd39f547b0b00fa184a440a1e44b96.tar.xz linux-4e37fd4d5dfd39f547b0b00fa184a440a1e44b96.zip | |
Merge branch 'pm-qos' into pm-cpuidle
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d79e9b3265b9..ab7629c5b856 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1629,9 +1629,9 @@ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, - <&cru SCLK_DPHY_TX0_CFG>; - clock-names = "ref", "pclk", "phy_cfg"; + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, + <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; + clock-names = "ref", "pclk", "phy_cfg", "grf"; power-domains = <&power RK3399_PD_VIO>; rockchip,grf = <&grf>; status = "disabled"; |