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| author | Chunyan Zhang <chunyan.zhang@unisoc.com> | 2020-04-14 12:16:36 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2020-05-21 11:50:44 +0200 |
| commit | 161af8fd02fd8bbade8d8c97e48ea7ba32704311 (patch) | |
| tree | 84b6453d75eb2698a853a4ec480f67a649f04eb2 /arch/arm64/boot/dts/sprd | |
| parent | arm64: dts: Add SC9863A clock nodes (diff) | |
| download | linux-161af8fd02fd8bbade8d8c97e48ea7ba32704311.tar.xz linux-161af8fd02fd8bbade8d8c97e48ea7ba32704311.zip | |
arm64: dts: Add SC9863A emmc and sd card nodes
Add emmc and sd card devicetree nodes for SC9863A.
Link: https://lore.kernel.org/r/20200414101636.24503-3-zhang.lyra@gmail.com
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm64/boot/dts/sprd')
| -rw-r--r-- | arch/arm64/boot/dts/sprd/sc9863a.dtsi | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi index 1ad6f6e95bca..8cf4a6575980 100644 --- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2019, Unisoc Inc. */ +#include <dt-bindings/clock/sprd,sc9863a-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "sharkl3.dtsi" @@ -543,5 +544,46 @@ }; }; }; + + ap-ahb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sdio0: sdio@20300000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20300000 0 0x1000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + + clock-names = "sdio", "enable"; + clocks = <&aon_clk CLK_SDIO0_2X>, + <&apahb_gate CLK_SDIO0_EB>; + assigned-clocks = <&aon_clk CLK_SDIO0_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <4>; + no-sdio; + no-mmc; + }; + + sdio3: sdio@20600000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20600000 0 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + + clock-names = "sdio", "enable"; + clocks = <&aon_clk CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>; + assigned-clocks = <&aon_clk CLK_EMMC_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + cap-mmc-hw-reset; + }; + }; }; }; |