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authorRoger Quadros <rogerq@kernel.org>2022-08-02 12:44:55 +0200
committerVignesh Raghavendra <vigneshr@ti.com>2022-09-01 12:08:44 +0200
commit5ec06904310da6441097c8f2d6e3fb196f42bca1 (patch)
tree1d6e94d9d0b5711f3f4efa41d4ab8a2d72277dc6 /arch/arm64/boot/dts/ti/k3-am64-main.dtsi
parentarm64: dts: ti: k3-j721e-main: fix RNG node clock id (diff)
downloadlinux-5ec06904310da6441097c8f2d6e3fb196f42bca1.tar.xz
linux-5ec06904310da6441097c8f2d6e3fb196f42bca1.zip
arm64: dts: ti: k3-am64-main: Add GPMC memory controller node
The GPMC is a unified memory controller dedicated for interfacing with external memory devices like - Asynchronous SRAM-like memories and ASICs - Asynchronous, synchronous, and page mode burst NOR flash - NAND flash - Pseudo-SRAM devices Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20220802104456.11069-2-rogerq@kernel.org
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-am64-main.dtsi')
-rw-r--r--arch/arm64/boot/dts/ti/k3-am64-main.dtsi19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 744629cb6725..14238bac71e7 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1328,4 +1328,23 @@
status = "disabled"; /* Used by OP-TEE */
};
};
+
+ gpmc0: memory-controller@3b000000 {
+ compatible = "ti,am64-gpmc";
+ power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 80 0>;
+ clock-names = "fck";
+ reg = <0x00 0x03b000000 0x00 0x400>,
+ <0x00 0x050000000 0x00 0x8000000>;
+ reg-names = "cfg", "data";
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ gpmc,num-cs = <3>;
+ gpmc,num-waitpins = <2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};