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| author | Sekhar Nori <nsekhar@ti.com> | 2020-08-02 18:53:56 +0200 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2020-08-31 13:31:24 +0200 |
| commit | 269a5641b1ed0ac00e9d75b43985407b34540d77 (patch) | |
| tree | ec572e449ce60dd1b2abb49ddd5c1104659ea6f7 /arch/arm64/boot/dts/ti/k3-j721e.dtsi | |
| parent | arm64: dts: ti: k3-j721e-som-p0: Reserve memory for IPC between RTOS cores (diff) | |
| download | linux-269a5641b1ed0ac00e9d75b43985407b34540d77.tar.xz linux-269a5641b1ed0ac00e9d75b43985407b34540d77.zip | |
arm64: dts: ti: k3-am65: restrict PCIe to Gen2 speed
Per errata i2104 documented in AM65x device errata document (TI document
number SPRZ452E, revised June 2019), Gen3 operation is not supported for
both PCIe Root Complex and Endpoint modes of operation.
See: https://www.ti.com/lit/er/sprz452e/sprz452e.pdf
Restrict speed to Gen2 to address the errata.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20200802165356.10285-1-nsekhar@ti.com
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-j721e.dtsi')
0 files changed, 0 insertions, 0 deletions