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| author | Sinthu Raja <sinthu.raja@ti.com> | 2023-09-21 12:00:37 +0200 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2023-10-05 17:14:41 +0200 |
| commit | b024d1a853b7bc8e2e01aa9a219d81a9df1a2ceb (patch) | |
| tree | e21039481290a9903fa098bf9961fb5452dfcb2e /arch/arm64/boot/dts/ti/k3-serdes.h | |
| parent | arm64: dts: ti: k3-am69-sk: Add DDR carveout memory nodes for C71x DSP (diff) | |
| download | linux-b024d1a853b7bc8e2e01aa9a219d81a9df1a2ceb.tar.xz linux-b024d1a853b7bc8e2e01aa9a219d81a9df1a2ceb.zip | |
arm64: dts: ti: Add USB Type C swap defines for J721S2 SoC
Lanes 0 and 2 of the J721S2 SerDes WIZ are reserved for USB type-C
lane swap. Update the macro definition for it.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230921100039.19897-2-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-serdes.h')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-serdes.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h index 29167f85c1f6..21b4886c47ba 100644 --- a/arch/arm64/boot/dts/ti/k3-serdes.h +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -111,7 +111,7 @@ #define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 #define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J721S2_SERDES0_LANE2_USB_SWAP 0x2 #define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 #define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 |