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| author | Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> | 2023-06-05 13:23:58 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-07-10 12:04:49 +0200 |
| commit | 3011e0c8139323af4e449bb4c7dce63aedc33808 (patch) | |
| tree | 3d0313f669f03748101fa0e1bac24c21f5ecdebd /arch/arm64/boot/dts/xilinx | |
| parent | Linux 6.5-rc1 (diff) | |
| download | linux-3011e0c8139323af4e449bb4c7dce63aedc33808.tar.xz linux-3011e0c8139323af4e449bb4c7dce63aedc33808.zip | |
arm64: zynqmp: Add L2 cache nodes
Describe SoC L2 cache hierarchy.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/130e5a6acbee94809b63a61cde5450fbff88cc9c.1685964230.git.michal.simek@amd.com
Diffstat (limited to 'arch/arm64/boot/dts/xilinx')
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 02cfcc716936..394db49ac6cb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -33,6 +33,7 @@ operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -42,6 +43,7 @@ reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu2: cpu@2 { @@ -51,6 +53,7 @@ reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu3: cpu@3 { @@ -60,6 +63,13 @@ reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; }; idle-states { |