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| author | Michal Simek <michal.simek@amd.com> | 2023-05-02 15:35:51 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-05-16 14:50:15 +0200 |
| commit | 5be4fbbfbec320dfb08530f0297fa2fe7aa1e836 (patch) | |
| tree | ae3667f2fa8dc940bdd218bfa77808659a2f8825 /arch/arm64/boot/dts/xilinx | |
| parent | arm64: zynqmp: Describe bus-width for SD card on KV260 (diff) | |
| download | linux-5be4fbbfbec320dfb08530f0297fa2fe7aa1e836.tar.xz linux-5be4fbbfbec320dfb08530f0297fa2fe7aa1e836.zip | |
arm64: zynqmp: Add phase tags marking
bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT.
That's why add it also to Linux to be aligned with bootloader requirement.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/48b554aef75d11e6ad2ef7d21f22accb35432112.1683034376.git.michal.simek@amd.com
Diffstat (limited to 'arch/arm64/boot/dts/xilinx')
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 6 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 3 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12 |
3 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 581221fdadf1..719ea5d5ae88 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -11,30 +11,35 @@ #include <dt-bindings/clock/xlnx-zynqmp-clk.h> / { pss_ref_clk: pss_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -43,6 +48,7 @@ &zynqmp_firmware { zynqmp_clk: clock-controller { + bootph-all; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 3f8a7a497f3e..464e28bf078a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -236,17 +236,20 @@ &i2c1 { status = "okay"; + bootph-all; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ + bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ + bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 44e0ab8aae53..850b497d7a81 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -118,6 +118,7 @@ }; zynqmp_ipi: zynqmp_ipi { + bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; @@ -127,6 +128,7 @@ ranges; ipi_mailbox_pmu1: mailbox@ff9905c0 { + bootph-all; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, @@ -143,6 +145,7 @@ dcc: dcc { compatible = "arm,dcc"; status = "disabled"; + bootph-all; }; pmu { @@ -164,8 +167,10 @@ compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; method = "smc"; + bootph-all; zynqmp_power: zynqmp-power { + bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; @@ -245,6 +250,7 @@ amba: axi { compatible = "simple-bus"; + bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; @@ -684,6 +690,7 @@ }; qspi: spi@ff0f0000 { + bootph-all; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; @@ -730,6 +737,7 @@ }; sdhci0: mmc@ff160000 { + bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -744,6 +752,7 @@ }; sdhci1: mmc@ff170000 { + bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -836,6 +845,7 @@ }; uart0: serial@ff000000 { + bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; @@ -846,6 +856,7 @@ }; uart1: serial@ff010000 { + bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; @@ -967,6 +978,7 @@ }; zynqmp_dpsub: display@fd4a0000 { + bootph-all; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, |