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| author | Jun Nie <jun.nie@linaro.org> | 2017-03-21 09:52:59 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2017-03-24 09:16:50 +0100 |
| commit | 25798d52b87d7c7d775dc7985817592f0ef3dffd (patch) | |
| tree | 105c1a9e625e7904e6f6636fa91d7687299d4f5a /arch/arm64/boot/dts/zte | |
| parent | arm64: dts: zte: remove zx296718 pll_vga clock (diff) | |
| download | linux-25798d52b87d7c7d775dc7985817592f0ef3dffd.tar.xz linux-25798d52b87d7c7d775dc7985817592f0ef3dffd.zip | |
arm64: dts: zte: add mmc devices for zx296718
Add three mmc devices for zx296718 SoC, and enable the SD and eMMMC on
zx296718-evb board.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts/zte')
| -rw-r--r-- | arch/arm64/boot/dts/zte/zx296718-evb.dts | 8 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/zte/zx296718.dtsi | 66 |
2 files changed, 74 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/zte/zx296718-evb.dts b/arch/arm64/boot/dts/zte/zx296718-evb.dts index e164ff6de5fc..238311b4cf0f 100644 --- a/arch/arm64/boot/dts/zte/zx296718-evb.dts +++ b/arch/arm64/boot/dts/zte/zx296718-evb.dts @@ -59,6 +59,14 @@ }; +&emmc { + status = "okay"; +}; + +&sd1 { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi index 1f256495b902..30d007b6ab6c 100644 --- a/arch/arm64/boot/dts/zte/zx296718.dtsi +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi @@ -298,6 +298,51 @@ status = "disabled"; }; + sd0: mmc@1110000 { + compatible = "zte,zx296718-dw-mshc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x01110000 0x1000>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + fifo-depth = <32>; + data-addr = <0x200>; + fifo-watermark-aligned; + bus-width = <4>; + clock-frequency = <50000000>; + clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>; + clock-names = "biu", "ciu"; + num-slots = <1>; + max-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; + status = "disabled"; + }; + + sd1: mmc@1111000 { + compatible = "zte,zx296718-dw-mshc"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x01111000 0x1000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + fifo-depth = <32>; + data-addr = <0x200>; + fifo-watermark-aligned; + bus-width = <4>; + clock-frequency = <167000000>; + clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>; + clock-names = "biu", "ciu"; + num-slots = <1>; + max-frequency = <167000000>; + cap-sdio-irq; + cap-sd-highspeed; + status = "disabled"; + }; + dma: dma-controller@1460000 { compatible = "zte,zx296702-dma"; reg = <0x01460000 0x1000>; @@ -332,6 +377,27 @@ reg = <0x1463000 0x1000>; }; + emmc: mmc@1470000{ + compatible = "zte,zx296718-dw-mshc"; + reg = <0x01470000 0x1000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + zte,aon-syscon = <&aon_sysctrl>; + bus-width = <8>; + fifo-depth = <128>; + data-addr = <0x200>; + fifo-watermark-aligned; + clock-frequency = <167000000>; + clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>; + clock-names = "biu", "ciu"; + max-frequency = <167000000>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + disable-wp; + status = "disabled"; + }; + audiocrm: clock-controller@1480000 { compatible = "zte,zx296718-audiocrm"; reg = <0x01480000 0x1000>; |