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| author | Neil Armstrong <narmstrong@baylibre.com> | 2016-10-05 15:53:50 +0200 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2016-10-18 18:35:56 +0200 |
| commit | 214ec5230d216763d0448c6a747a50cef64bcff6 (patch) | |
| tree | 48a80307cdd39a6e9d725f03f2969c176a91ba52 /arch/arm64/boot/dts | |
| parent | ARM64: dts: meson-gxbb: Add support for the Nexbox A95X Board (diff) | |
| download | linux-214ec5230d216763d0448c6a747a50cef64bcff6.tar.xz linux-214ec5230d216763d0448c6a747a50cef64bcff6.zip | |
ARM64: dts: meson-gx: Add missing L2 cache node
In order to remove the boot warning :
[ 2.290933] Unable to detect cache hierarchy from DT for CPU 0
And add missing L2 cache hierarchy information, add a simple l2 cache node
and reference it from the A53 cpu nodes.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm64/boot/dts')
| -rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 0737056b369f..a6cd953ef7e1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -64,6 +64,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -71,6 +72,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -78,6 +80,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -85,6 +88,11 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; }; }; |