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authorRajendra Nayak <rnayak@codeaurora.org>2020-01-07 11:45:26 +0100
committerBjorn Andersson <bjorn.andersson@linaro.org>2020-02-26 05:52:55 +0100
commit83e5e33eaba2df888cfd5a2cd9319c0637ebc93d (patch)
treef78ffc6001bca0428dba24c3520ac978240641ce /arch/arm64/boot/dts
parentarm64: dts: qcom: sc7180: Add CPU capacity values (diff)
downloadlinux-83e5e33eaba2df888cfd5a2cd9319c0637ebc93d.tar.xz
linux-83e5e33eaba2df888cfd5a2cd9319c0637ebc93d.zip
arm64: dts: qcom: sc7180: Add CPU topology
SC7180 has 2 big cores and 6 LITTLE ones in a single cluster with shared L3. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1578393926-5052-3-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts')
-rw-r--r--arch/arm64/boot/dts/qcom/sc7180.dtsi36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index c754b4bf3273..97cfc113c9b3 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -214,6 +214,42 @@
next-level-cache = <&L3_0>;
};
};
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+
+ core6 {
+ cpu = <&CPU6>;
+ };
+
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
};
memory@80000000 {