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| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2015-06-04 11:19:02 +0200 |
|---|---|---|
| committer | Andy Gross <agross@codeaurora.org> | 2015-07-28 23:19:13 +0200 |
| commit | c4da5a561627da156d7ce322be70e6f342db654d (patch) | |
| tree | d3354d9b262b409d3fe89ab6edced69d7419e286 /arch/arm64/boot | |
| parent | arm64: dts: qcom: Add msm8916 BLSP device nodes (diff) | |
| download | linux-c4da5a561627da156d7ce322be70e6f342db654d.tar.xz linux-c4da5a561627da156d7ce322be70e6f342db654d.zip | |
arm64: dts: qcom: Add msm8916 sdhci configuration nodes
Add sdhci1 and sdhci2 device configuration nodes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: Andy Gross <agross@codeaurora.org>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8916.dtsi | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 6681c6558d97..9ff0eb47777b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -24,7 +24,10 @@ #address-cells = <2>; #size-cells = <2>; - aliases { }; + aliases { + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + }; chosen { }; @@ -236,6 +239,35 @@ status = "disabled"; }; + sdhc_1: sdhci@07824000 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x07824900 0x11c>, <0x07824000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + bus-width = <8>; + non-removable; + status = "disabled"; + }; + + sdhc_2: sdhci@07864000 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x07864900 0x11c>, <0x07864000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + bus-width = <4>; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; |