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| author | Rajendra Nayak <rnayak@codeaurora.org> | 2020-01-07 11:45:24 +0100 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2020-02-26 05:52:55 +0100 |
| commit | 71f873169a80729f1b5efeae88e84b5beafa73cb (patch) | |
| tree | 97e7238e378dcdf6ed5d95af9385658e0b7d50f2 /arch/arm64/boot | |
| parent | arm64: dts: Add ipq6018 SoC and CP01 board support (diff) | |
| download | linux-71f873169a80729f1b5efeae88e84b5beafa73cb.tar.xz linux-71f873169a80729f1b5efeae88e84b5beafa73cb.zip | |
arm64: dts: qcom: sc7180: Add dynamic CPU power coefficients
Add dynamic power coefficients for Silver and Gold CPUs on
SC7180 SoC.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1578393926-5052-1-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 2f1b3a1d92ea..8ebfa2e2741d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -89,6 +89,7 @@ compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -106,6 +107,7 @@ compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_100>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -120,6 +122,7 @@ compatible = "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_200>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -134,6 +137,7 @@ compatible = "arm,armv8"; reg = <0x0 0x300>; enable-method = "psci"; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_300>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -148,6 +152,7 @@ compatible = "arm,armv8"; reg = <0x0 0x400>; enable-method = "psci"; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_400>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -162,6 +167,7 @@ compatible = "arm,armv8"; reg = <0x0 0x500>; enable-method = "psci"; + dynamic-power-coefficient = <100>; next-level-cache = <&L2_500>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -176,6 +182,7 @@ compatible = "arm,armv8"; reg = <0x0 0x600>; enable-method = "psci"; + dynamic-power-coefficient = <405>; next-level-cache = <&L2_600>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -190,6 +197,7 @@ compatible = "arm,armv8"; reg = <0x0 0x700>; enable-method = "psci"; + dynamic-power-coefficient = <405>; next-level-cache = <&L2_700>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; |