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| author | James Morse <james.morse@arm.com> | 2019-10-17 19:42:59 +0200 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2019-10-25 18:48:44 +0200 |
| commit | ee9d90be9ddace01b7fb126567e4b539fbe1f82f (patch) | |
| tree | e0776d49cff3e0ff4259ee3c853c64d6bce31c3d /arch/arm64/include/asm/cache.h | |
| parent | arm64: errata: Hide CTR_EL0.DIC on systems affected by Neoverse-N1 #1542419 (diff) | |
| download | linux-ee9d90be9ddace01b7fb126567e4b539fbe1f82f.tar.xz linux-ee9d90be9ddace01b7fb126567e4b539fbe1f82f.zip | |
arm64: Fake the IminLine size on systems affected by Neoverse-N1 #1542419
Systems affected by Neoverse-N1 #1542419 support DIC so do not need to
perform icache maintenance once new instructions are cleaned to the PoU.
For the errata workaround, the kernel hides DIC from user-space, so that
the unnecessary cache maintenance can be trapped by firmware.
To reduce the number of traps, produce a fake IminLine value based on
PAGE_SIZE.
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cache.h')
| -rw-r--r-- | arch/arm64/include/asm/cache.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 43da6dd29592..806e9dc2a852 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -11,6 +11,7 @@ #define CTR_L1IP_MASK 3 #define CTR_DMINLINE_SHIFT 16 #define CTR_IMINLINE_SHIFT 0 +#define CTR_IMINLINE_MASK 0xf #define CTR_ERG_SHIFT 20 #define CTR_CWG_SHIFT 24 #define CTR_CWG_MASK 15 @@ -18,7 +19,7 @@ #define CTR_DIC_SHIFT 29 #define CTR_CACHE_MINLINE_MASK \ - (0xf << CTR_DMINLINE_SHIFT | 0xf << CTR_IMINLINE_SHIFT) + (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT) #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) |