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| author | Vincenzo Frascino <vincenzo.frascino@arm.com> | 2019-09-06 11:58:01 +0200 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2020-09-03 18:26:32 +0200 |
| commit | 3b714d24ef173f81c78af16f73dcc9b40428c803 (patch) | |
| tree | 355afb2207944284b1e3d2a14a89083f57ddef98 /arch/arm64/include/asm/cpucaps.h | |
| parent | arm64: mte: Use Normal Tagged attributes for the linear map (diff) | |
| download | linux-3b714d24ef173f81c78af16f73dcc9b40428c803.tar.xz linux-3b714d24ef173f81c78af16f73dcc9b40428c803.zip | |
arm64: mte: CPU feature detection and initial sysreg configuration
Add the cpufeature and hwcap entries to detect the presence of MTE. Any
secondary CPU not supporting the feature, if detected on the boot CPU,
will be parked.
Add the minimum SCTLR_EL1 and HCR_EL2 bits for enabling MTE. The Normal
Tagged memory type is configured in MAIR_EL1 before the MMU is enabled
in order to avoid disrupting other CPUs in the CnP domain.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Co-developed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cpucaps.h')
| -rw-r--r-- | arch/arm64/include/asm/cpucaps.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 07b643a70710..1937653b05a3 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -64,7 +64,8 @@ #define ARM64_BTI 54 #define ARM64_HAS_ARMv8_4_TTL 55 #define ARM64_HAS_TLB_RANGE 56 +#define ARM64_MTE 57 -#define ARM64_NCAPS 57 +#define ARM64_NCAPS 58 #endif /* __ASM_CPUCAPS_H */ |