diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2019-04-09 17:22:24 +0200 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2019-10-08 13:25:25 +0200 |
| commit | 9405447ef79bc93101373e130f72e9e6cbf17dbb (patch) | |
| tree | 32b2849bdfb5da0850e377da453de5c3b50476ff /arch/arm64/include/asm/cpucaps.h | |
| parent | arm64: Enable workaround for Cavium TX2 erratum 219 when running SMT (diff) | |
| download | linux-9405447ef79bc93101373e130f72e9e6cbf17dbb.tar.xz linux-9405447ef79bc93101373e130f72e9e6cbf17dbb.zip | |
arm64: Avoid Cavium TX2 erratum 219 when switching TTBR
As a PRFM instruction racing against a TTBR update can have undesirable
effects on TX2, NOP-out such PRFM on cores that are affected by
the TX2-219 erratum.
Cc: <stable@vger.kernel.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include/asm/cpucaps.h')
| -rw-r--r-- | arch/arm64/include/asm/cpucaps.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index e81e0cbd728f..ac1dbca3d0cd 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -53,7 +53,8 @@ #define ARM64_HAS_DCPODP 43 #define ARM64_WORKAROUND_1463225 44 #define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45 +#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46 -#define ARM64_NCAPS 46 +#define ARM64_NCAPS 47 #endif /* __ASM_CPUCAPS_H */ |