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| author | Anshuman Khandual <anshuman.khandual@arm.com> | 2023-06-14 08:59:41 +0200 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2023-06-14 15:37:33 +0200 |
| commit | dae169fd63f323b4dea1a01beb46c558e10315ac (patch) | |
| tree | 7562b858586b43825b5e52f5b0cfba2299e283f7 /arch/arm64/include/asm/sysreg.h | |
| parent | arm64/sysreg: Rename TRBMAR_EL1 fields per auto-gen tools format (diff) | |
| download | linux-dae169fd63f323b4dea1a01beb46c558e10315ac.tar.xz linux-dae169fd63f323b4dea1a01beb46c558e10315ac.zip | |
arm64/sysreg: Rename TRBTRG_EL1 fields per auto-gen tools format
This renames TRBTRG_EL1 register fields per auto-gen tools format without
causing any functional change in the TRBE driver.
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: kvmarm@lists.linux.dev
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230614065949.146187-7-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/sysreg.h')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index ef8c9d81b6ad..0ba0f268ac79 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -267,8 +267,8 @@ #define TRBMAR_EL1_SH_SHIFT 8 #define TRBMAR_EL1_Attr_MASK GENMASK(7, 0) #define TRBMAR_EL1_Attr_SHIFT 0 -#define TRBTRG_TRG_MASK GENMASK(31, 0) -#define TRBTRG_TRG_SHIFT 0 +#define TRBTRG_EL1_TRG_MASK GENMASK(31, 0) +#define TRBTRG_EL1_TRG_SHIFT 0 #define TRBIDR_FLAG BIT(5) #define TRBIDR_PROG BIT(4) #define TRBIDR_ALIGN_MASK GENMASK(3, 0) |