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| author | Suzuki K. Poulose <suzuki.poulose@arm.com> | 2015-10-19 15:19:37 +0200 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2015-10-19 18:55:12 +0200 |
| commit | 44eaacf1b8999b15cec89bd9d9cd989da4798d53 (patch) | |
| tree | 08d4afb61baa16d41c98fb9035c54d9d788a48dd /arch/arm64/include/asm/thread_info.h | |
| parent | arm64: Add page size to the kernel image header (diff) | |
| download | linux-44eaacf1b8999b15cec89bd9d9cd989da4798d53.tar.xz linux-44eaacf1b8999b15cec89bd9d9cd989da4798d53.zip | |
arm64: Add 16K page size support
This patch turns on the 16K page support in the kernel. We
support 48bit VA (4 level page tables) and 47bit VA (3 level
page tables).
With 16K we can map 128 entries using contiguous bit hint
at level 3 to map 2M using single TLB entry.
TODO: 16K supports 32 contiguous entries at level 2 to get us
1G(which is not yet supported by the infrastructure). That should
be a separate patch altogether.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Jeremy Linton <jeremy.linton@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Steve Capper <steve.capper@linaro.org>
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/thread_info.h')
| -rw-r--r-- | arch/arm64/include/asm/thread_info.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h index 5eac6a2300af..90c7ff233735 100644 --- a/arch/arm64/include/asm/thread_info.h +++ b/arch/arm64/include/asm/thread_info.h @@ -25,6 +25,8 @@ #ifdef CONFIG_ARM64_4K_PAGES #define THREAD_SIZE_ORDER 2 +#elif defined(CONFIG_ARM64_16K_PAGES) +#define THREAD_SIZE_ORDER 0 #endif #define THREAD_SIZE 16384 |