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| author | Andrew Murray <andrew.murray@arm.com> | 2019-04-09 11:52:42 +0200 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2019-04-16 17:27:36 +0200 |
| commit | d16ed4105f5bbd8a34f15053045a6657f4c52c6f (patch) | |
| tree | f1dc8f77d945d60531642802f4def8e5ee303d3b /arch/arm64/include | |
| parent | arm64: HWCAP: encapsulate elf_hwcap (diff) | |
| download | linux-d16ed4105f5bbd8a34f15053045a6657f4c52c6f.tar.xz linux-d16ed4105f5bbd8a34f15053045a6657f4c52c6f.zip | |
arm64: Handle trapped DC CVADP
The ARMv8.5 DC CVADP instruction may be trapped to EL1 via
SCTLR_EL1.UCI therefore let's provide a handler for it.
Just like the CVAP instruction we use a 'sys' instruction instead of
the 'dc' alias to avoid build issues with older toolchains.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include')
| -rw-r--r-- | arch/arm64/include/asm/esr.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index 3541720189c9..0e27fe91d5ea 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -196,9 +196,10 @@ /* * User space cache operations have the following sysreg encoding * in System instructions. - * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0) + * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) */ #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 +#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 |