diff options
| author | Mark Brown <broonie@kernel.org> | 2022-07-04 19:03:02 +0200 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-07-05 12:45:48 +0200 |
| commit | 3bbeca99309fd795f8697648e59fec8b70209f6e (patch) | |
| tree | f2d2a5d52acd63d1feb52aba880fe619b6385e51 /arch/arm64/include | |
| parent | arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generation (diff) | |
| download | linux-3bbeca99309fd795f8697648e59fec8b70209f6e.tar.xz linux-3bbeca99309fd795f8697648e59fec8b70209f6e.zip | |
arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation
Convert ID_AA64ZFR0_EL1 to automatic register generation as per DDI0487H.a,
no functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-29-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 2e2b5811e081..d7f115368197 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -192,7 +192,6 @@ #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) -#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) @@ -737,28 +736,6 @@ #define ID_AA64PFR1_MTE 0x2 #define ID_AA64PFR1_MTE_ASYMM 0x3 -/* id_aa64zfr0 */ -#define ID_AA64ZFR0_EL1_F64MM_SHIFT 56 -#define ID_AA64ZFR0_EL1_F32MM_SHIFT 52 -#define ID_AA64ZFR0_EL1_I8MM_SHIFT 44 -#define ID_AA64ZFR0_EL1_SM4_SHIFT 40 -#define ID_AA64ZFR0_EL1_SHA3_SHIFT 32 -#define ID_AA64ZFR0_EL1_BF16_SHIFT 20 -#define ID_AA64ZFR0_EL1_BitPerm_SHIFT 16 -#define ID_AA64ZFR0_EL1_AES_SHIFT 4 -#define ID_AA64ZFR0_EL1_SVEver_SHIFT 0 - -#define ID_AA64ZFR0_EL1_F64MM_IMP 0x1 -#define ID_AA64ZFR0_EL1_F32MM_IMP 0x1 -#define ID_AA64ZFR0_EL1_I8MM_IMP 0x1 -#define ID_AA64ZFR0_EL1_BF16_IMP 0x1 -#define ID_AA64ZFR0_EL1_SM4_IMP 0x1 -#define ID_AA64ZFR0_EL1_SHA3_IMP 0x1 -#define ID_AA64ZFR0_EL1_BitPerm_IMP 0x1 -#define ID_AA64ZFR0_EL1_AES_IMP 0x1 -#define ID_AA64ZFR0_EL1_AES_PMULL128 0x2 -#define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1 - /* id_aa64mmfr0 */ #define ID_AA64MMFR0_ECV_SHIFT 60 #define ID_AA64MMFR0_FGT_SHIFT 56 |