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| author | Will Deacon <will.deacon@arm.com> | 2018-08-07 14:53:41 +0200 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2018-09-14 18:46:22 +0200 |
| commit | b8925ee2e12d1cb9a11d6f28b5814f2bfa59dce1 (patch) | |
| tree | 0f65bfc029abec901e6770e120e85a98a216c5b4 /arch/arm64/kernel/cpu_errata.c | |
| parent | KVM: arm64: Set SCTLR_EL2.DSSBS if SSBD is forcefully disabled and !vhe (diff) | |
| download | linux-b8925ee2e12d1cb9a11d6f28b5814f2bfa59dce1.tar.xz linux-b8925ee2e12d1cb9a11d6f28b5814f2bfa59dce1.zip | |
arm64: cpu: Move errata and feature enable callbacks closer to callers
The cpu errata and feature enable callbacks are only called via their
respective arm64_cpu_capabilities structure and therefore shouldn't
exist in the global namespace.
Move the PAN, RAS and cache maintenance emulation enable callbacks into
the same files as their corresponding arm64_cpu_capabilities structures,
making them static in the process.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/kernel/cpu_errata.c')
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index c063490d7b51..8900cb0615f8 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -433,6 +433,12 @@ out_printmsg: } #endif /* CONFIG_ARM64_SSBD */ +static void __maybe_unused +cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) +{ + sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); +} + #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ .matches = is_affected_midr_range, \ .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) |