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| author | Will Deacon <will@kernel.org> | 2022-07-25 11:57:37 +0200 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-07-25 11:57:37 +0200 |
| commit | 618ff55eec8d1b772e2f84f9d46866b43a2063cf (patch) | |
| tree | 8f1b686fe8e697225fd4d18cb50b0c053bdf9d6c /arch/arm64/kernel/cpu_errata.c | |
| parent | Merge branch 'for-next/stacktrace' into for-next/core (diff) | |
| parent | arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation (diff) | |
| download | linux-618ff55eec8d1b772e2f84f9d46866b43a2063cf.tar.xz linux-618ff55eec8d1b772e2f84f9d46866b43a2063cf.zip | |
Merge branch 'for-next/sysregs' into for-next/core
* for-next/sysregs: (28 commits)
arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation
arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generation
arm64/sysreg: Convert LORID_EL1 to automatic generation
arm64/sysreg: Convert LORC_EL1 to automatic generation
arm64/sysreg: Convert LORN_EL1 to automatic generation
arm64/sysreg: Convert LOREA_EL1 to automatic generation
arm64/sysreg: Convert LORSA_EL1 to automatic generation
arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation
arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation
arm64/sysreg: Convert GMID to automatic generation
arm64/sysreg: Convert DCZID_EL0 to automatic generation
arm64/sysreg: Convert CTR_EL0 to automatic generation
arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition names
arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names
arm64/sysreg: Remove defines for RPRES enumeration
arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields
arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums
arm64/sysreg: Standardise naming for WFxT defines
arm64/sysreg: Make BHB clear feature defines match the architecture
arm64/sysreg: Align pointer auth enumeration defines with architecture
...
Diffstat (limited to 'arch/arm64/kernel/cpu_errata.c')
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index aa9609e6ca67..7e6289e709fc 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -187,7 +187,7 @@ has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, int scope) { u32 midr = read_cpuid_id(); - bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT); + bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT); const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); |