diff options
| author | Will Deacon <will.deacon@arm.com> | 2016-07-25 17:17:52 +0200 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2017-01-10 15:27:56 +0100 |
| commit | b20d1ba3cf4b99dc47ea3e1102399e4728386783 (patch) | |
| tree | f5784c903abb5cfbeb721e66485e27fbe160377c /arch/arm64/kernel/cpufeature.c | |
| parent | arm64: Remove useless UAO IPI and describe how this gets enabled (diff) | |
| download | linux-b20d1ba3cf4b99dc47ea3e1102399e4728386783.tar.xz linux-b20d1ba3cf4b99dc47ea3e1102399e4728386783.zip | |
arm64: cpufeature: allow for version discrepancy in PMU implementations
Perf already supports multiple PMU instances for heterogeneous systems,
so there's no need to be strict in the cpufeature checking, particularly
as the PMU extension is optional in the architecture.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 99f56983c415..d9714adb6a2a 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -184,7 +184,11 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), - S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), + /* + * We can instantiate multiple PMU instances with different levels + * of support. + * */ + S_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), ARM64_FTR_END, |