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| author | James Morse <james.morse@arm.com> | 2022-11-30 18:16:14 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-12-01 16:53:14 +0100 |
| commit | c6e155e8e561dafcba9faf86598d7ec69942ab86 (patch) | |
| tree | 09b399def5f5c8d54c3d5cbb144e1c3df288a646 /arch/arm64/kernel/cpufeature.c | |
| parent | arm64/sysreg: Standardise naming for MVFR1_EL1 (diff) | |
| download | linux-c6e155e8e561dafcba9faf86598d7ec69942ab86.tar.xz linux-c6e155e8e561dafcba9faf86598d7ec69942ab86.zip | |
arm64/sysreg: Standardise naming for MVFR2_EL1
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the MVFR2_EL1 register use lower-case for feature
names where the arm-arm does the same.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-16-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c56339066304..935579e5517a 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -453,8 +453,8 @@ static const struct arm64_ftr_bits ftr_mvfr1[] = { }; static const struct arm64_ftr_bits ftr_mvfr2[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), ARM64_FTR_END, }; |