diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2014-06-06 15:16:21 +0200 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2014-07-04 17:16:52 +0200 |
| commit | 974c8e450b9327a03453a4a450a2030b1bd42b5f (patch) | |
| tree | c0e2539e84fe0b169ebd350368ca0b6da543ae53 /arch/arm64/kernel/head.S | |
| parent | arm64: mm: Make icache synchronisation logic huge page aware (diff) | |
| download | linux-974c8e450b9327a03453a4a450a2030b1bd42b5f.tar.xz linux-974c8e450b9327a03453a4a450a2030b1bd42b5f.zip | |
arm64: fix el2_setup check of CurrentEL
The CurrentEL system register reports the Current Exception Level
of the CPU. It doesn't say anything about the stack handling, and
yet we compare it to PSR_MODE_EL2t and PSR_MODE_EL2h.
It works by chance because PSR_MODE_EL2t happens to match the right
bits, but that's otherwise a very bad idea. Just check for the EL
value instead.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[catalin.marinas@arm.com: fixed arch/arm64/kernel/efi-entry.S]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/kernel/head.S | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index a96d3a6a63f6..a2c1195abb7f 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -270,8 +270,7 @@ ENDPROC(stext) */ ENTRY(el2_setup) mrs x0, CurrentEL - cmp x0, #PSR_MODE_EL2t - ccmp x0, #PSR_MODE_EL2h, #0x4, ne + cmp x0, #CurrentEL_EL2 b.ne 1f mrs x0, sctlr_el2 CPU_BE( orr x0, x0, #(1 << 25) ) // Set the EE bit for EL2 |