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| author | Mark Rutland <mark.rutland@arm.com> | 2016-08-08 12:12:07 +0200 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2016-08-22 11:00:48 +0200 |
| commit | 0a7d87a7776e2616334473c4209e277b6ca300e5 (patch) | |
| tree | a12bbd3d31a938b31f35720ee3e9c85f2b301dee /arch/arm64/kernel/hibernate-asm.S | |
| parent | Linux 4.8-rc3 (diff) | |
| download | linux-0a7d87a7776e2616334473c4209e277b6ca300e5.tar.xz linux-0a7d87a7776e2616334473c4209e277b6ca300e5.zip | |
arm64: hibernate: reduce TLB maintenance scope
In break_before_make_ttbr_switch we perform broadcast TLB maintenance
for the inner shareable domain, and use a DSB ISH to complete this.
However, at the point we execute this, secondary CPUs are either
physically offline, or executing code outside of the kernel. Upon
entering the kernel, secondary CPUs will invalidate their TLBs before
enabling their MMUs.
Thus we do not need to invalidate TLBs of other CPUs, and as with
idmap_cpu_replace_ttbr1 we can reduce the scope of maintenance to the
TLBs of the local CPU. This keeps our TLB maintenance code consistent,
and is a minor optimisation.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: James Morse <james.morse@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel/hibernate-asm.S')
| -rw-r--r-- | arch/arm64/kernel/hibernate-asm.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/kernel/hibernate-asm.S b/arch/arm64/kernel/hibernate-asm.S index 46f29b6560ec..7734f3e7a1be 100644 --- a/arch/arm64/kernel/hibernate-asm.S +++ b/arch/arm64/kernel/hibernate-asm.S @@ -36,8 +36,8 @@ .macro break_before_make_ttbr_switch zero_page, page_table msr ttbr1_el1, \zero_page isb - tlbi vmalle1is - dsb ish + tlbi vmalle1 + dsb nsh msr ttbr1_el1, \page_table isb .endm |