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| author | Andre Przywara <andre.przywara@arm.com> | 2016-06-28 19:07:28 +0200 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2016-07-01 12:26:20 +0200 |
| commit | 290622efc76ece22ef76a30bf117755891ab27f6 (patch) | |
| tree | 565b544e4d178c78ab32d1246f5585ec922074c9 /arch/arm64/mm/cache.S | |
| parent | Revert "arm64: alternatives: add enable parameter to conditional asm macros" (diff) | |
| download | linux-290622efc76ece22ef76a30bf117755891ab27f6.tar.xz linux-290622efc76ece22ef76a30bf117755891ab27f6.zip | |
arm64: fix "dc cvau" cache operation on errata-affected core
The ARM errata 819472, 826319, 827319 and 824069 for affected
Cortex-A53 cores demand to promote "dc cvau" instructions to
"dc civac" as well.
Attribute the usage of the instruction in __flush_cache_user_range
to also be covered by our alternative patching efforts.
For that we introduce an assembly macro which both deals with
alternatives while still tagging the instructions as USER.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/mm/cache.S')
| -rw-r--r-- | arch/arm64/mm/cache.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 50ff9ba3a236..07d7352d7c38 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -52,7 +52,7 @@ ENTRY(__flush_cache_user_range) sub x3, x2, #1 bic x4, x0, x3 1: -USER(9f, dc cvau, x4 ) // clean D line to PoU +user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE add x4, x4, x2 cmp x4, x1 b.lo 1b |