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| author | Catalin Marinas <catalin.marinas@arm.com> | 2012-03-05 12:49:27 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2012-09-17 14:41:56 +0200 |
| commit | c1cc1552616d0f354d040823151e61634e7ad01f (patch) | |
| tree | 7c9118864bba9fd78aaec954e2f5269dbbc68240 /arch/arm64/mm/pgd.c | |
| parent | arm64: MMU definitions (diff) | |
| download | linux-c1cc1552616d0f354d040823151e61634e7ad01f.tar.xz linux-c1cc1552616d0f354d040823151e61634e7ad01f.zip | |
arm64: MMU initialisation
This patch contains the initialisation of the memory blocks, MMU
attributes and the memory map. Only five memory types are defined:
Device nGnRnE (equivalent to Strongly Ordered), Device nGnRE (classic
Device memory), Device GRE, Normal Non-cacheable and Normal Cacheable.
Cache policies are supported via the memory attributes register
(MAIR_EL1) and only affect the Normal Cacheable mappings.
This patch also adds the SPARSEMEM_VMEMMAP initialisation.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm64/mm/pgd.c')
0 files changed, 0 insertions, 0 deletions