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| author | Christoffer Dall <christoffer.dall@linaro.org> | 2017-11-06 16:49:26 +0100 |
|---|---|---|
| committer | Christoffer Dall <christoffer.dall@linaro.org> | 2017-11-06 16:49:26 +0100 |
| commit | 80f77e54f18c6a16c54797fd4b3d3b454d6f560c (patch) | |
| tree | dc58df7e472da7d4240226a5c98c68ccf3a73dce /arch/arm64 | |
| parent | KVM: arm/arm64: fix the incompatible matching for external abort (diff) | |
| parent | Merge tag 'irqchip-4.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/m... (diff) | |
| download | linux-80f77e54f18c6a16c54797fd4b3d3b454d6f560c.tar.xz linux-80f77e54f18c6a16c54797fd4b3d3b454d6f560c.zip | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/Kconfig | 19 | ||||
| -rw-r--r-- | arch/arm64/include/asm/arch_gicv3.h | 5 |
2 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0df64a6a56d4..22455e4168c1 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -539,6 +539,25 @@ config QCOM_QDF2400_ERRATUM_0065 If unsure, say Y. + +config SOCIONEXT_SYNQUACER_PREITS + bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" + default y + help + Socionext Synquacer SoCs implement a separate h/w block to generate + MSI doorbell writes with non-zero values for the device ID. + + If unsure, say Y. + +config HISILICON_ERRATUM_161600802 + bool "Hip07 161600802: Erroneous redistributor VLPI base" + default y + help + The HiSilicon Hip07 SoC usees the wrong redistributor base + when issued ITS commands such as VMOVP and VMAPP, and requires + a 128kB offset to be applied to the target address in this commands. + + If unsure, say Y. endmenu diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index b7e3f74822da..9becba9ab392 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -87,6 +87,11 @@ static inline void gic_write_ctlr(u32 val) isb(); } +static inline u32 gic_read_ctlr(void) +{ + return read_sysreg_s(SYS_ICC_CTLR_EL1); +} + static inline void gic_write_grpen1(u32 val) { write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1); |