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authorArnd Bergmann <arnd@arndb.de>2016-11-30 17:57:26 +0100
committerArnd Bergmann <arnd@arndb.de>2016-11-30 17:57:26 +0100
commit7b88f1a4896ca7e8a490218af69077ade1ae43e4 (patch)
tree5d8054f1225cde2a62d604d5c472bc19da9f58a6 /arch/arm64
parentMerge tag 'tegra-for-4.10-arm64-dt-numeric-ids' of git://git.kernel.org/pub/s... (diff)
parentMerge tag 'bcm2835-dt-64-next-2016-11-18' into devicetree-arm64/next (diff)
downloadlinux-7b88f1a4896ca7e8a490218af69077ade1ae43e4.tar.xz
linux-7b88f1a4896ca7e8a490218af69077ade1ae43e4.zip
Merge tag 'arm-soc/for-4.10/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64
Pull "Broadcom devicetree-arm64 changes for 4.10" from Florian Fainelli: This pull request contains Broadcom ARM64 based SoC Device Tree changes for 4.10, please pull the following: - Robin updates the Northstart 2 DTS to use the generic IOMMU binding - Scott renames the Broadcom Northstar 2 binding document to use a standard name including the brcm vendor prefix - Kamal adds the QSPI Device Tree node to the Northstar 2 SoC and updates the Northstar 2 SVK reference board DTS file with it enabled. - Rob adds the Device Tree node for the Broadcom PDC (mailbox) hardware to the Northstar 2 SoC - Jon enables the SDIO1 block and adds proper PCIe PHYs Device Tree nodes to the Northstar 2 SoC - Ray adds required properties NAND controller properties to make NAND work on the Northstar 2 SVK board, this was submitted as a 4.9 fixes and is included here to resolve DTS file merges - Andrea removes an incorrect power LED from the Raspberry Pi 3 DTS - Andreas fixes the compatible string for the BCM2837 (Raspberry Pi 3) - Eric defines standard pinctrl groups in the BCM2835 GPIO node - Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes to use their appropriate pinctrl functions - Linus adds names for the Raspberry Pi GPIO lines based on the datasheet - Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block - Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and Device Tree nodes he also uses the proper DTSI file to define the USB host mode for the USB Device Tree nodes * tag 'arm-soc/for-4.10/devicetree-arm64' of http://github.com/Broadcom/stblinux: (23 commits) arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 ARM64: dts: bcm2837-rpi-3-b: remove incorrect pwr LED ARM64: bcm2835: dts: add thermal node to device-tree of bcm2837 ARM: bcm2835: Add names for the Raspberry Pi GPIO lines ARM: bcm2835: dts: add thermal node to device-tree of bcm283x dt: bindings: add thermal device driver for bcm2835 arm64: dts: Add Broadcom Northstar2 device tree entries for PDC driver. ARM: dts: bcm283x: fix typo in mailbox address DT: binding: bcm2835-mbox: fix address typo in example ARM64: dts: bcm2835: Fix bcm2837 compatible string arm64: dts: Update Broadcom NS2 to generic IOMMU binding arm64: dts: Updated NAND DT properties for NS2 SVK arm64: dts: rename ns2.txt to brcm,ns2.txt ARM64: dts: Add QSPI Device Tree node for NS2 ARM64: dts: bcm283x: Use dtsi for USB host mode ARM: dts: bcm283x: drop alt3 from &gpio ARM: dts: bcm283x: add pinctrl group to &sdhci, drop pins from &gpio ARM: dts: bcm283x: add pinctrl group to &i2c1, drop pins from &gpio ARM: dts: bcm283x: add pinctrl group to &i2c0, drop pins from &gpio ...
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts8
-rw-r--r--arch/arm64/boot/dts/broadcom/bcm2837.dtsi8
l---------arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi1
-rw-r--r--arch/arm64/boot/dts/broadcom/ns2-svk.dts38
-rw-r--r--arch/arm64/boot/dts/broadcom/ns2.dtsi62
5 files changed, 108 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
index 7841b724e340..c309633a1e87 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
+++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
@@ -2,6 +2,7 @@
#include "bcm2837.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
+#include "bcm283x-rpi-usb-host.dtsi"
/ {
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
@@ -15,13 +16,6 @@
act {
gpios = <&gpio 47 0>;
};
-
- pwr {
- label = "PWR";
- gpios = <&gpio 35 0>;
- default-state = "keep";
- linux,default-trigger = "default-on";
- };
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
index 8216bbb29fe0..19f2fe620a21 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
@@ -1,7 +1,7 @@
#include "bcm283x.dtsi"
/ {
- compatible = "brcm,bcm2836";
+ compatible = "brcm,bcm2837";
soc {
ranges = <0x7e000000 0x3f000000 0x1000000>,
@@ -74,3 +74,9 @@
interrupt-parent = <&local_intc>;
interrupts = <8>;
};
+
+/* enable thermal sensor with the correct compatible property set */
+&thermal {
+ compatible = "brcm,bcm2837-thermal";
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi
new file mode 120000
index 000000000000..cbeebe312ff8
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi
@@ -0,0 +1 @@
+../../../../arm/boot/dts/bcm283x-rpi-usb-host.dtsi \ No newline at end of file
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
index b09f3bc5c6c1..34619079a6c6 100644
--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -157,6 +157,10 @@
status = "ok";
};
+&sdio1 {
+ status = "ok";
+};
+
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
@@ -187,3 +191,37 @@
groups = "nand_grp";
};
};
+
+&qspi {
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <12500000>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x000a0000>;
+ };
+
+ partition@a0000 {
+ label = "env";
+ reg = <0x000a0000 0x00060000>;
+ };
+
+ partition@100000 {
+ label = "system";
+ reg = <0x00100000 0x00600000>;
+ };
+
+ partition@700000 {
+ label = "rootfs";
+ reg = <0x00700000 0x01900000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index d95dc408629a..863503d78f57 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -133,6 +133,9 @@
status = "disabled";
+ phys = <&pci_phy0>;
+ phy-names = "pcie-phy";
+
msi-parent = <&msi0>;
msi0: msi@20020000 {
compatible = "brcm,iproc-msi";
@@ -171,6 +174,9 @@
status = "disabled";
+ phys = <&pci_phy1>;
+ phy-names = "pcie-phy";
+
msi-parent = <&msi4>;
msi4: msi@50020000 {
compatible = "brcm,iproc-msi";
@@ -191,6 +197,42 @@
#include "ns2-clock.dtsi"
+ pdc0: iproc-pdc0@612c0000 {
+ compatible = "brcm,iproc-pdc-mbox";
+ reg = <0x612c0000 0x445>; /* PDC FS0 regs */
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ brcm,rx-status-len = <32>;
+ brcm,use-bcm-hdr;
+ };
+
+ pdc1: iproc-pdc1@612e0000 {
+ compatible = "brcm,iproc-pdc-mbox";
+ reg = <0x612e0000 0x445>; /* PDC FS1 regs */
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ brcm,rx-status-len = <32>;
+ brcm,use-bcm-hdr;
+ };
+
+ pdc2: iproc-pdc2@61300000 {
+ compatible = "brcm,iproc-pdc-mbox";
+ reg = <0x61300000 0x445>; /* PDC FS2 regs */
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ brcm,rx-status-len = <32>;
+ brcm,use-bcm-hdr;
+ };
+
+ pdc3: iproc-pdc3@61320000 {
+ compatible = "brcm,iproc-pdc-mbox";
+ reg = <0x61320000 0x445>; /* PDC FS3 regs */
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ brcm,rx-status-len = <32>;
+ brcm,use-bcm-hdr;
+ };
+
dma0: dma@61360000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x61360000 0x1000>;
@@ -248,7 +290,7 @@
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- mmu-masters;
+ #iommu-cells = <1>;
};
pinctrl: pinctrl@6501d130 {
@@ -565,5 +607,23 @@
brcm,nand-has-wp;
};
+
+ qspi: spi@66470200 {
+ compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
+ reg = <0x66470200 0x184>,
+ <0x66470000 0x124>,
+ <0x67017408 0x004>,
+ <0x664703a0 0x01c>;
+ reg-names = "mspi", "bspi", "intr_regs",
+ "intr_status_reg";
+ interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "spi_l1_intr";
+ clocks = <&iprocmed>;
+ clock-names = "iprocmed";
+ num-cs = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
};
};