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authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>2018-03-09 13:09:38 +0100
committerSimon Horman <horms+renesas@verge.net.au>2018-05-16 10:44:32 +0200
commit55cda28160e1ea852955ee17464d0dccfa67fa72 (patch)
treed76942294413eda474a47fb46f27415b500daca1 /arch/arm64
parentarm64: dts: renesas: condor: add SCIF0 pins (diff)
downloadlinux-55cda28160e1ea852955ee17464d0dccfa67fa72.tar.xz
linux-55cda28160e1ea852955ee17464d0dccfa67fa72.zip
arm64: dts: renesas: condor: add EtherAVB pins
Add the (previously omitted) EtherAVB pin data to the Condor board's device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77980-condor.dts8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
index 38f11cee42dc..7af5afa41795 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -30,6 +30,9 @@
};
&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
renesas,no-ether-link;
@@ -50,6 +53,11 @@
};
&pfc {
+ avb_pins: avb {
+ groups = "avb_mdio", "avb_rgmii";
+ function = "avb";
+ };
+
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";