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| author | Stephen Boyd <sboyd@codeaurora.org> | 2016-01-09 00:57:09 +0100 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2016-02-24 07:14:02 +0100 |
| commit | 0a9bcf4e09c098d14b3a07a7782c4cc24cde21dd (patch) | |
| tree | 4a6f49cfbfbf970a565a75d41853b5b19b9235ab /arch/arm64 | |
| parent | arm64: dts: Rename qcom,gcc node to clock-controller (diff) | |
| download | linux-0a9bcf4e09c098d14b3a07a7782c4cc24cde21dd.tar.xz linux-0a9bcf4e09c098d14b3a07a7782c4cc24cde21dd.zip | |
arm64: dts: Add L2 cache node to msm8916
The msm8916 SoC has an L2 cache for all 4 CPUs. Add it to the
dtsi file so that the cache hierarchy can be probed.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8916.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index ba8184d0f948..42573a7d4a94 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -61,24 +61,33 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0>; + next-level-cache = <&L2_0>; }; CPU1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x1>; + next-level-cache = <&L2_0>; }; CPU2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x2>; + next-level-cache = <&L2_0>; }; CPU3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x3>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; }; }; |