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authorThierry Reding <treding@nvidia.com>2015-09-09 16:25:05 +0200
committerThierry Reding <treding@nvidia.com>2015-11-24 16:52:24 +0100
commit9e71045f1b770cd609509fc77fe19f84281d0b78 (patch)
treed8221459865809cfce1a34bc7235e6dd7ea5f50d /arch/arm64
parentarm64: tegra: Add NVIDIA P2571 board support (diff)
downloadlinux-9e71045f1b770cd609509fc77fe19f84281d0b78.tar.xz
linux-9e71045f1b770cd609509fc77fe19f84281d0b78.zip
arm64: tegra: Add NVIDIA Jetson TX1 support
The NVIDIA Jetson TX1 is a processor module that features a Tegra210 SoC with 4 GiB of LPDDR4 RAM attached, a 32 GiB eMMC and other essentials. It is typically connected to some I/O board (such as the P2597) that has the connectors needed to hook it up to the outside world. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi45
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
new file mode 100644
index 000000000000..2b7f88950d1e
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
@@ -0,0 +1,45 @@
+#include "tegra210.dtsi"
+
+/ {
+ model = "NVIDIA Jetson TX1";
+ compatible = "nvidia,p2180", "nvidia,tegra210";
+
+ aliases {
+ rtc1 = "/rtc@0,7000e000";
+ serial0 = &uarta;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x1 0x0>;
+ };
+
+ /* debug port */
+ serial@0,70006000 {
+ status = "okay";
+ };
+
+ pmc@0,7000e400 {
+ nvidia,invert-interrupt;
+ };
+
+ /* eMMC */
+ sdhci@0,700b0600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};