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authorLinus Torvalds <torvalds@linux-foundation.org>2015-05-17 00:33:25 +0200
committerLinus Torvalds <torvalds@linux-foundation.org>2015-05-17 00:33:25 +0200
commitd66102706621949e3ac7db14448eb65ea2abfcaa (patch)
treebb6673b8973958d9f63d684324712c211d8069ec /arch/arm64
parentMerge branch 'for-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang... (diff)
parentMerge tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/... (diff)
downloadlinux-d66102706621949e3ac7db14448eb65ea2abfcaa.tar.xz
linux-d66102706621949e3ac7db14448eb65ea2abfcaa.zip
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann: "Nothing frightening this time, just smaller fixes in a number of places. The other changes contained here are: MAINTAINERS file updates: - The mach-gemini maintainer is back in action and has a new git tree - Krzysztof Kozlowski has volunteered to be a new co-maintainer for the samsung platforms - updates to the files that belong to Marvell mvebu Bug fixes: - The largest changes are on omap2, but are only to avoid some harmless warnings and to fix reset on omap4 - a small regression fix on tegra - multiple fixes for incorrect IRQ affinity on vexpress - the missing system controller on arm64 juno is added - one revert of a patch that was accidentally applied twice for mach-rockchip - two clock related DT fixes for mvebu - a workaround for suspend with old DT binaries on new exynos kernels - Another fix for suspend on exynos, needs to be backported" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (21 commits) MAINTAINERS: Add dts entries for some of the Marvell SoCs MAINTAINERS: ARM: EXYNOS: Add Krzysztof Kozlowski as co-maintainer ARM: EXYNOS: Use of_machine_is_compatible instead of soc_is_exynos4 ARM: EXYNOS: Fix failed second suspend on Exynos4 Revert "ARM: rockchip: fix undefined instruction of reset_ctrl_regs" ARM: EXYNOS: Fix dereference of ERR_PTR returned by of_genpd_get_from_provider ARM: EXYNOS: Don't try to initialize suspend on old DT ARM: dts: Add keep-power-in-suspend to WiFi SDIO node for Peach Boards ARM: gemini: fix compiler warning due wrong data type ARM: vexpress/tc2: Add interrupt-affinity to the PMU node ARM: vexpress/ca9: Add interrupt-affinity to the PMU node ARM: vexpress/ca9: Add unified-cache property to l2 cache node ARM64: juno: add sp810 support and fix sp804 clock frequency ARM: Gemini: Maintainers update ARM: OMAP2+: Remove bogus struct clk comparison for timer clock ARM: dove: Add clock-names to CuBox Si5351 clk generator ARM: AM33xx+: hwmod: re-use omap4 implementations for reset functionality ARM: OMAP4+: PRM: add support for passing status register/bit info to reset ARM: AM43xx: hwmod: add VPFE hwmod entries ARM: mvebu: Fix the main PLL frequency on Armada 375, 38x and 39x SoCs ...
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/arm/juno-motherboard.dtsi31
1 files changed, 27 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
index c138b95a8356..351c95bda89e 100644
--- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
@@ -21,6 +21,20 @@
clock-output-names = "juno_mb:clk25mhz";
};
+ v2m_refclk1mhz: refclk1mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000>;
+ clock-output-names = "juno_mb:refclk1mhz";
+ };
+
+ v2m_refclk32khz: refclk32khz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "juno_mb:refclk32khz";
+ };
+
motherboard {
compatible = "arm,vexpress,v2p-p1", "simple-bus";
#address-cells = <2>; /* SMB chipselect number and offset */
@@ -66,6 +80,15 @@
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
+ v2m_sysctl: sysctl@020000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x020000 0x1000>;
+ clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
+ clock-names = "refclk", "timclk", "apb_pclk";
+ #clock-cells = <1>;
+ clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
+ };
+
mmci@050000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>;
@@ -106,16 +129,16 @@
compatible = "arm,sp804", "arm,primecell";
reg = <0x110000 0x10000>;
interrupts = <9>;
- clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
- clock-names = "timclken1", "apb_pclk";
+ clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
+ clock-names = "timclken1", "timclken2", "apb_pclk";
};
v2m_timer23: timer@120000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x120000 0x10000>;
interrupts = <9>;
- clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
- clock-names = "timclken1", "apb_pclk";
+ clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
+ clock-names = "timclken1", "timclken2", "apb_pclk";
};
rtc@170000 {