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| author | David Gilhooley <dgilhooley@nvidia.com> | 2018-05-09 00:49:43 +0200 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-05-09 15:28:28 +0200 |
| commit | 0583a4ef05987f7e0f3a7bdd3365e5dc36ca306d (patch) | |
| tree | 60fb0ab820d29916e53ac73ece33bd7f72a12622 /arch/arm64 | |
| parent | arm64: Add MIDR encoding for NVIDIA CPUs (diff) | |
| download | linux-0583a4ef05987f7e0f3a7bdd3365e5dc36ca306d.tar.xz linux-0583a4ef05987f7e0f3a7bdd3365e5dc36ca306d.zip | |
arm64: capabilities: Add NVIDIA Denver CPU to bp_harden list
The NVIDIA Denver CPU also needs a PSCI call to harden the branch
predictor.
Signed-off-by: David Gilhooley <dgilhooley@nvidia.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index a900befadfe8..e4a1182deff7 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -316,6 +316,7 @@ static const struct midr_range arm64_bp_harden_smccc_cpus[] = { MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1), MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR), + MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER), {}, }; |