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author | Miquel Raynal <miquel.raynal@free-electrons.com> | 2017-10-13 11:01:58 +0200 |
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committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2017-10-30 15:56:22 +0100 |
commit | 7c48dc201bf9aa8636716bccaa78f37a165e725b (patch) | |
tree | 62ca7d12b73d245ce24fc8effb46b82fc4359810 /arch/arm64 | |
parent | arm64: dts: marvell: armada-37xx: add UART clock (diff) | |
download | linux-7c48dc201bf9aa8636716bccaa78f37a165e725b.tar.xz linux-7c48dc201bf9aa8636716bccaa78f37a165e725b.zip |
arm64: dts: marvell: armada-37xx: add second UART port
Add a node in Armada 37xx DTSI file for the second UART, with a
different compatible due to its extended IP which has some
differences with the first UART already in place.
Make use of this commit to also fully describe the first port and
use the same clear and named interrupt bindings for both ports.
The standard UART (UART0) uses level-interrupts while the extended
UART (UART1) uses edge-triggered interrupts.
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r-- | arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index cddeb00a6e6d..90c26d616a54 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -55,6 +55,7 @@ aliases { serial0 = &uart0; + serial1 = &uart1; }; cpus { @@ -136,7 +137,22 @@ compatible = "marvell,armada-3700-uart"; reg = <0x12000 0x200>; clocks = <&xtalclk>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uart-sum", "uart-tx", "uart-rx"; + status = "disabled"; + }; + + uart1: serial@12200 { + compatible = "marvell,armada-3700-uart-ext"; + reg = <0x12200 0x30>; + clocks = <&xtalclk>; + interrupts = + <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "uart-tx", "uart-rx"; status = "disabled"; }; |